verilog HDLBits刷题[Shift Registers]“Exams/2014 q4b”---Shift register

📅 发布时间:2026/7/25 4:12:39
verilog HDLBits刷题[Shift Registers]“Exams/2014 q4b”---Shift register 1、题目Consider then-bit shift register circuit shown below:Write a top-level Verilog module (named top_module) for the shift register, assuming thatn 4. Instantiate four copies of your MUXDFF subcircuit in your top-level module. Assume that you are going to implement the circuit on the DE2 board.Connect theRinputs to theSWswitches,clktoKEY[0],EtoKEY[1],LtoKEY[2], andwtoKEY[3].Connect the outputs to the red lightsLEDR[3:0].(Reuse your MUXDFF from exams/2014_q4a.)2、代码module top_module ( input [3:0] SW, input [3:0] KEY, output [3:0] LEDR ); // MUXDFF inst0(KEY[0],LEDR[1],SW[0],KEY[1],KEY[2],LEDR[0]); MUXDFF inst1(KEY[0],LEDR[2],SW[1],KEY[1],KEY[2],LEDR[1]); MUXDFF inst2(KEY[0],LEDR[3],SW[2],KEY[1],KEY[2],LEDR[2]); MUXDFF inst3(KEY[0],KEY[3],SW[3],KEY[1],KEY[2],LEDR[3]); endmodule module MUXDFF( input clk, input w, R, E, L, output reg Q ); always (posedge clk) begin if(L) Q R; else if(E) Q w; else Q Q; end endmodule